This invention relates to a semiconductor memory device, such as an EEPROM or an EPROM, which has two or more gate electrode layers, and a method for manufacturing the device. More particularly, the invention relates to a semiconductor device which employs a metal of a high melting point and a low resistance or a silicide layer containing the metal as the material of a second electrode layer, so as to minimize a signal delay due to the long length of the gate electrode layer, and also to a method for manufacturing the device.
A method for manufacturing a memory cell with two gate layers employed, for example, in an EEPROM, in a process as shown in FIGS. 1A to 1C is well known.
Referring first to FIG. 1A, element isolating oxide layers 302 as element isolating regions are formed on surface portions of e.g., a p-type silicon substrate 301, then a first gate oxide film 303 is formed on that surface portion of the substrate which is located between the element isolating oxide layers 302, and a first polysilicon layer 304 which will constitute a first gate electrode (a floating gate) is formed on the overall surface of the resultant structure.
Referring then to FIG. 1B, the polysilicon layer 304 is patterned to form a floating gate 305, and subjected to a heat treatment, and then an insulating film 306 is deposited by the known LPCVD method.
Subsequently, as shown in FIG. 1C, a second polysilicon layer 307 which will constitute a second gate electrode (a control gate) is deposited on the overall surface of the structure, and further a tungsten silicide layer 308, for example, is deposited thereon.
FIG. 2A is a sectional view, taken along lines II--II of FIG. 1C. As is shown in FIG. 2A, the tungsten silicide layer 308, the second polysilicon layer 307, the insulating film 306, and the floating gate 305 are patterned to form a stacked gate 401 comprising the control gate and the completely isolated floating gate 305.
Subsequently, as is shown in FIG. 2B, an oxide film 311 is formed, and then ions of an n-type impurity are injected into the substrate 301, using the stacked gate 401 as a mask. The injected ions are activated to form n.sup.+ -type source and drain regions 403 and 404, thereby depositing an oxide film by the LPCVD, forming a contact hole and an Al wire layer. Thus, the EEPROM memory is completed.
The above-described semiconductor manufacturing method has the following drawbacks:
Since in the method, the first polysilicon layer 304 is formed on the overall surface of the structure and then patterned to form the floating gate 305, a trench 309 which divides the floating gate 305 is formed in the gate 305 at a location corresponding to each element isolating oxide layer 302, and the insulating film 306 is formed on the divided floating gate portions 305 and on that portion of the element isolating oxide layer 302 at which the trench 309 is formed.
Thereafter, a control gate of a double-layer structure which consists of the second polysilicon layer 307 and the high-melting-point metal layer (or the silicide layer containing the metal) 308 is formed in order to reduce the resistance of the control gate and increase the operational speed of the element.
The upper surface of the second polysilicon film 307 has irregularities corresponding to those of the underlayer structure which are formed because of the trenches 309 and the element isolating layer 302. The high-melting-point metal or silicide layer 308 deposited on the polysilicon layer 307 accordingly has irregularities at its upper surface corresponding to the irregularities of the underlayer structure.
When the resultant structure is heated in a later process, stress concentration may well occur at concave portions of the upper surface of the resultant structure, in particular, above the trenches 309. As a result, a crack 310 (see FIG. 1C) may occur in the silicide layer, thereby increasing the resistance of the silicide layer, or breaking the same.
Moreover, there is a case where a method described below will be employed at the time of patterning the control gate layers 307 and 308, the insulating film 306 and the floating gate 305, in order to prevent the so-called micro-loading effect (which indicates a state wherein a very fine pattern is hard to form by etching, which state may well occur in a recent highly-refining process). In this method, in place of performing etching using a conventional resist layer as a mask, an oxide film and a nitride film are deposited on a second electrode layer which will be patterned to form a control gate, and are patterned using a conventional resist layer. Thereafter, the resist layer is removed and the patterned oxide and nitride films are used as masks.
In the case of using this method, that part of the masks, which enters cracks caused due to the irregularities of the trenches 309, is hard to etch at the time of patterning. As a result, part of the mask materials will be left in the form of columns at the irregularities, and accordingly part of the material of the gate electrode will be left as a residue at the irregularities in the next etching treatment for forming the gate electrode. This means that the resultant memory cell cannot operate normally.
FIG. 3 is a plan view of a memory cell array. In FIG. 3, hatched portions 501 indicate cell regions of a semiconductor substrate provided with control gate electrodes 503 of a band shape and element isolating regions 502.
Reference numeral 504 denotes a conductive layer which cannot be removed by etching since part of the mask material is left as a residue in a crack formed in the element isolating regions 502. The conductive layer 504 makes the gates of adjacent memory cells shortcircuited.
Further, to meet the development of refining techniques, there is a case using a photoetching method for forming a fine resist pattern, where an antireflection film is provided below a resist layer to restrain reflection of light from an underlayer and enhance the resolution of the resist layer. If, in this case, however, the antireflection film has a high fluidity, the thickness of the film may well be varied between portions thereof because of steps formed of the underlayer, with the result that the film may be overetched or incompletely etched with an etching residue left.
In addition, to make, as flat as possible, the upper surfaces of those portions of the second polysilicon layer 307, which are located over the trenches 309 between the floating gates 305, U.S. Pat. No. 5,150,178, for example, discloses a method for depositing the second polysilicon layer 307 by a thickness equal to half or more the width of the trench 309, and a method for etching back the second polysilicon layer 307 by the RIE method.
Although, however, the above-mentioned methods can prevent the layer 307 from having a great step in the trench 309 if the floating gate 305 has a thin thickness, steps will be formed still between the trench 309 formed at a location corresponding to the element isolating region 302, the floating gate 305 and the insulating film 306. Thus, the polysilicon layer 307 is influenced by the irregularities of the underlayer between them. Accordingly, there is still a possibility of occurrence of a crack in the high-melting-point metal or silicide layer 308 deposited on the second polysilicon layer 307, because of the irregularities of the underlayer.
As described above, in the conventional memory cell of a multilayer gate structure, the drawback that a crack will occur in the uppermost gate layer because of a step formed of the underlayer still remains.